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SOLOMON SYSTECH
SEMICONDUCTOR TECHNICAL DATA
Product Preview LCD Segment / Common Driver with Controller
CMOS
SSD1812 is a single-chip CMOS LCD driver with controller for liquid crystal dotmatrix graphic display system. It consists of 187 high voltage driving output pins for driving 132 Segments, 54 Commons and 1 Icon Driving-Common.
SSD1812
TAB
SSD1812 displays data directly from its internal 132 X 65 bits Graphic Display Data RAM (GDDRAM). Data/Commands are sent from general MCU through a software selectable 6800-/8080-series compatible Parallel Interface or Serial Peripheral Interface. SSD1812 embeds a DC-DC Converter, an On-Chip Bias Divider and an On-Chip Oscillator which reduce the number of external components. With the special design on minimizing power consumption and die/package layout, SSD1812 is suitable for any portable battery-driven applications requiring a long operation period and a compact size.
Gold Bump Die
ORDERING INFORMATION SSD1812Z SSD1812TR Gold Bump Die TAB
* * * * * * * * * * * * * * * * * * *
Single Supply Operation, 1.8 V - 3.5V Minimum -12.0V LCD Driving Output Voltage Low Current Sleep Mode On-Chip Voltage Generator / External Power Supply 2X / 3X / 4X On-Chip DC-DC Converter On-Chip Oscillator Programmable Multiplex ratio [1Mux - 55Mux] On-Chip Smart Bias Divider Programmable 1/4, 1/5, 1/6, 1/7, 1/8 and 1/9 bias ratio 8-bit 6800-series Parallel Interface, 8-bit 8080-series Parallel Interface and Serial Peripheral Interface On-Chip 132 x 65 Graphic Display Data RAM Re-mapping of Row and Column Drivers Vertical Scrolling Display Offset Control RAM Page Blinking 64 Level Internal Contrast Control External Contrast Control Selectable LCD Driving Voltage Temperature Coefficients (8 settings) Available in Gold Bump Die and Standard TAB (Tape Automated Bonding) Package
This document contains information on a new product under development. Solomon reserves the right to change or discontinue this product without notice.
Copyright (c) 1999 Solomon Technolgoy Corp.
REV 1.2 12/99
Block Diagram
ICONS
ROW0 to ROW63
SEG0~SEG131
HV Buffer Cell Level Shifter
Level Selector
VL6 VL2 VDD Display Timing Generator VF LCD Driving Voltage Generator 2X / 3X / 4X DC/DC Converter, Voltage Regulator, Smart Bias Divider, Contrast Control, Temperature Compensation VEE C1P C2P C1N C2N C3N IRS HPM VFS VSS1
187 Bit Latch MSTAT M
DOF M/S
CL CLS
Oscillator
GDDRAM 132 X 65 Bits
Command Decoder
VSS VDD Command Interface Parallel / Serial Interface
RES P/S CS1 CS2 D/C
R/W C68/80 M/S E (RD) (WR)
D7 D6 D5 D4 D3 D2 D1 D 0 (SDA) (SCK)
SSD1812 2
REV 1.2 12/99
SOLOMON
178 177 176 175
Dummy /CS1 /RES D/C R/W(/WR) D0 (SDA) D1 (SCK) D2 D3 D4 D5 D6 D7 VDD VSS VEE C3N C1P C1N C2N C2P VL2 VL3 VL4 VL5 VL6 VF P/S Dummy
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
:: :: ::
Dummy Dummy Dummy ICONS ROW58 ROW57 R0W56
153 152 151 150 149 148
ROW34 ROW33 ROW32 SEG95 SEG94 SEG93
:: :: ::
57 56 55 54 53 52
SEG2 SEG1 SEG0 ROW0 ROW1 ROW2
:: :: ::
30 29 28
ROW24 ROW25 ROW26 Dummy Dummy Dummy
SSD1812T Pin Assignment (Copper View)
SOLOMON
REV 1.2 12/99
SSD1812 3
ICONS ROW0 ROW1 ROW2 ROW3 ROW4 ROW5 ROW6 ROW7 ROW8 ROW9 ROW10 ROW11 ROW12 ROW13 ROW14 ROW15 ROW16 ROW17 ROW18 ROW19 SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20
137 Center: 3816.05, 305.2 Size: 100.1u x 100.1u
115 Center: 3819.2, -419.2 Size: 99.75u x 99.75u
: :
SEG110 SEG111 SEG112 SEG113 SEG114 SEG115 SEG116 SEG117 SEG118 SEG119 SEG120 SEG121 SEG122 SEG123 SEG124 SEG125 SEG126 SEG127 SEG128 SEG129 SEG130 SEG131
: :
268
1
ROW20 ROW21 : : ROW30 ROW31 VDD IRS VSS /HPM VDD P/S C68/80 VSS CLS M/S VDD NC NC VDD VDD VF VF VL6 VL6 VL6 VL5 VL5 VL4 VL4 VL4 VL3 VL3 VL3 VL2 VL2 VDD VDD VFS VFS VSS VSS C2P C2P C2P C2N C2N C2N C2N C1N C1N C1N C1P C1P C1P C3N C3N C3N C3N VEE VEE VEE VEE VSS1 VSS1 VSS1 VSS1 VSS VSS VSS VDD VDD VDD VDD D7 (SDA) D6 (SCK) D5 D4 D3 D2 D1 D0 VDD E(/RD) R/W(/WR) VSS D/C /RES VDD CS2 /CS1 VSS /DOF CL M MSTAT NC ICONS ROW63 ROW62 ROW61 : : ROW54 ROW53
Center: 3701.075, -304.5 Radius: 50.925u
Gold Bump Alignment Mark This alignment mark contains gold nump for IC bumping process alignment and IC identifications. No conductive tracks should be laid underneath this mark to avoid short circuit.
Note: Coordinates and Size of all alignment marks are in unit um and w.r.t. center of the chip.
Y
Center: -3380.625, 205.625 Size: 99.75u x 99.75u
(0,0)
Center: 389.725, -201.6 Radius: 27.125u
x
PIN #1 Die Size: 10.977mm X 1.912mm Die Thickness: 533 +/-25um Bump Pitch: 76.2 um [Min] Bump Height: Nominal 18um
SSD1812Z Die Pin Assignment SOLOMON
SSD1812 4
REV 1.2 12/99
ROW32 ROW33 ROW34 ROW35 ROW36 ROW37 ROW38 ROW39 ROW40 ROW41 ROW42 ROW43 ROW44 ROW45 ROW46 ROW47 ROW48 ROW49 ROW50 ROW51 ROW52
Table 1. ROW pins assignment for COM signals in Programmable Multiplex Ratio [On power-on-reset, SSD1812 is set to 54 Multiplex]
Die Pad Name ROW0 ROW1 ROW2 ROW3 ROW4 ROW5 ROW6 ROW7 ROW8 ROW9 ROW10 ROW11 ROW12 ROW13 ROW14 ROW15 ROW16 ROW17 ROW18 ROW19 ROW20 ROW21 ROW22 ROW23 ROW24 ROW25 ROW26 ROW27 ROW28 ROW29 ROW30 ROW31 ROW32 ROW33 ROW34 ROW35 ROW36 ROW37 ROW38 ROW39 ROW40 ROW41 ROW42 ROW43 ROW44 ROW45 ROW46 ROW47 ROW48 ROW49 ROW50 ROW51 ROW52 ROW53 ROW54 ROW55 ROW56 ROW57 ROW58 ROW59 ROW60 ROW61 ROW62 ROW63 54 Mux Com Signal Output COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 COM17 COM18 COM19 COM20 COM21 COM22 COM23 COM24 COM25 COM26 NC NC NC NC NC COM27 COM28 COM29 COM30 COM31 COM32 COM33 COM34 COM35 COM36 COM37 COM38 COM39 COM40 COM41 COM42 COM43 COM44 COM45 COM46 COM47 COM48 COM49 COM50 COM51 COM52 COM53 NC NC NC NC NC 53 Mux Com Signal Output COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 COM17 COM18 COM19 COM20 COM21 COM22 COM23 COM24 COM25 COM26 NC NC NC NC NC COM27 COM28 COM29 COM30 COM31 COM32 COM33 COM34 COM35 COM36 COM37 COM38 COM39 COM40 COM41 COM42 COM43 COM44 COM45 COM46 COM47 COM48 COM49 COM50 COM51 COM52 NON-SELECT* NC NC NC NC NC 52 Mux Com Signal Output 51 Mux Com Signal Output NON-SELECT* NON-SELECT* COM0 COM0 COM1 COM1 COM2 COM2 COM3 COM3 COM4 COM4 COM5 COM5 COM6 COM6 COM7 COM7 COM8 COM8 COM9 COM9 COM10 COM10 COM11 COM11 COM12 COM12 COM13 COM13 COM14 COM14 COM15 COM15 COM16 COM16 COM17 COM17 COM18 COM18 COM19 COM19 COM20 COM20 COM21 COM21 COM22 COM22 COM23 COM23 COM24 COM24 COM25 COM25 NC NC NC NC NC NC NC NC NC NC COM26 COM26 COM27 COM27 COM28 COM28 COM29 COM29 COM30 COM30 COM31 COM31 COM32 COM32 COM33 COM33 COM34 COM34 COM35 COM35 COM36 COM36 COM37 COM37 COM38 COM38 COM39 COM39 COM40 COM40 COM41 COM41 COM42 COM42 COM43 COM43 COM44 COM44 COM45 COM45 COM46 COM46 COM47 COM47 COM48 COM48 COM49 COM49 COM50 COM50 COM51 NON-SELECT* NON-SELECT* NON-SELECT* NC NC NC NC NC NC NC NC NC NC 48 Mux Com Signal Output NON-SELECT* NON-SELECT* NON-SELECT* COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 COM17 COM18 COM19 COM20 COM21 COM22 COM23 NC NC NC NC NC COM24 COM25 COM26 COM27 COM28 COM29 COM30 COM31 COM32 COM33 COM34 COM35 COM36 COM37 COM38 COM39 COM40 COM41 COM42 COM43 COM44 COM45 COM46 COM47 NON-SELECT* NON-SELECT* NON-SELECT* NC NC NC NC NC 47 Mux Com Signal Output NON-SELECT* NON-SELECT* NON-SELECT* COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 COM17 COM18 COM19 COM20 COM21 COM22 COM23 NC NC NC NC NC COM24 COM25 COM26 COM27 COM28 COM29 COM30 COM31 COM32 COM33 COM34 COM35 COM36 COM37 COM38 COM39 COM40 COM41 COM42 COM43 COM44 COM45 COM46 NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NC NC NC NC NC 34 Mux Com Signal Output NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 NC NC NC NC NC COM17 COM18 COM19 COM20 COM21 COM22 COM23 COM24 COM25 COM26 COM27 COM28 COM29 COM30 COM31 COM32 COM33 NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NC NC NC NC NC 33 Mux Com Signal Output NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 NC NC NC NC NC COM17 COM18 COM19 COM20 COM21 COM22 COM23 COM24 COM25 COM26 COM27 COM28 COM29 COM30 COM31 COM32 NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NC NC NC NC NC 32 Mux Com Signal Output NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 NC NC NC NC NC COM16 COM17 COM18 COM19 COM20 COM21 COM22 COM23 COM24 COM25 COM26 COM27 COM28 COM29 COM30 COM31 NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NC NC NC NC NC
Remark: * The ROW will output a Non-Select COM signal. * NC = No Connection.
SOLOMON
REV 1.2 12/99
SSD1812 5
SSD1812Z Die Pad Coordinates
PAD # NAME 1 ROW53 2 ROW54 3 ROW55 4 ROW56 5 ROW57 6 ROW58 7 ROW59 8 ROW60 9 ROW61 10 ROW62 11 ROW63 12 ICONS 13 NC 14 MSTAT 15 M 16 CL 17 /DOF 18 VSS 19 /CS1 20 CS2 21 VDD 22 /RES 23 D/C 24 VSS 25 R /W 26 E /RD 27 VDD 28 D0 29 D1 30 D2 31 D3 32 D4 33 D5 34 D6 35 D7 36 VDD 37 VDD 38 VDD 39 VDD 40 VSS 41 VSS 42 VSS 43 VSS1 44 VSS1 45 VSS1 46 VSS1 47 VEE 48 VEE 49 VEE 50 VEE 51 C3N 52 C3N 53 C3N 54 C3N 55 C1P 56 C1P 57 C1P 58 C1N 59 C1N 60 C1N 10.977mm D ie Size: Bump Size: Pad # X [um] 1 - 12 43.5 13 - 103 61.7 104 - 115 43.5
X -4958.45 -4882.15 -4805.85 -4729.55 -4653.25 -4576.95 -4500.65 -4424.35 -4348.05 -4271.75 -4195.45 -4119.15 -4000.50 -3911.60 -3822.70 -3733.80 -3644.90 -3556.00 -3467.10 -3378.20 -3289.30 -3200.40 -3111.50 -3022.60 -2933.70 -2844.80 -2755.90 -2667.00 -2578.10 -2489.20 -2400.30 -2311.40 -2222.50 -2133.60 -2044.70 -1955.80 -1866.90 -1778.00 -1689.10 -1600.20 -1511.30 -1422.40 -1333.50 -1244.60 -1155.70 -1066.80 -977.90 -889.00 -800.10 -711.20 -622.30 -533.40 -444.50 -355.60 -266.70 -177.80 -88.90 0.00 88.90 177.80 X Y [um] 101.6 61.7 101.6
Y -751.98 -751.98 -751.98 -751.98 -751.98 -751.98 -751.98 -751.98 -751.98 -751.98 -751.98 -751.98 -771.93 -771.93 -771.93 -771.93 -771.93 -771.93 -771.93 -771.93 -771.93 -771.93 -771.93 -771.93 -771.93 -771.93 -771.93 -771.93 -771.93 -771.93 -771.93 -771.93 -771.93 -771.93 -771.93 -771.93 -771.93 -771.93 -771.93 -771.93 -771.93 -771.93 -771.93 -771.93 -771.93 -771.93 -771.93 -771.93 -771.93 -771.93 -771.93 -771.93 -771.93 -771.93 -771.93 -771.93 -771.93 -771.93 -771.93 -771.93 1.912mm Pad # 116 - 136
PAD # 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115
NAME C2N C2N C2N C2N C2P C2P C2P VSS VSS VFS VFS VDD VDD VL2 VL2 VL3 VL3 VL3 VL4 VL4 VL4 VL5 VL5 VL6 VL6 VL6 VF VF VDD VDD NC NC VDD M /S CLS VSS C68/80 P/S VDD /HPM VSS IRS VDD ROW31 ROW30 ROW29 ROW28 ROW27 ROW26 ROW25 ROW24 ROW23 ROW22 ROW21 ROW20
X 266.70 355.60 444.50 533.40 622.30 711.20 800.10 889.00 977.90 1066.80 1155.70 1244.60 1333.50 1422.40 1511.30 1600.20 1689.10 1778.00 1866.90 1955.80 2044.70 2133.60 2222.50 2311.40 2400.30 2489.20 2578.10 2667.00 2755.90 2844.80 2933.70 3022.60 3111.50 3200.40 3289.30 3378.20 3467.10 3556.00 3644.90 3733.80 3822.70 3911.60 4000.50 4119.15 4195.45 4271.75 4348.05 4424.35 4500.65 4576.95 4653.25 4729.55 4805.85 4882.15 4958.45
Y -771.93 -771.93 -771.93 -771.93 -771.93 -771.93 -771.93 -771.93 -771.93 -771.93 -771.93 -771.93 -771.93 -771.93 -771.93 -771.93 -771.93 -771.93 -771.93 -771.93 -771.93 -771.93 -771.93 -771.93 -771.93 -771.93 -771.93 -771.93 -771.93 -771.93 -771.93 -771.93 -771.93 -771.93 -771.93 -771.93 -771.93 -771.93 -771.93 -771.93 -771.93 -771.93 -771.93 -751.98 -751.98 -751.98 -751.98 -751.98 -751.98 -751.98 -751.98 -751.98 -751.98 -751.98 -751.98
PAD # 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136
NAME ROW19 ROW18 ROW17 ROW16 ROW15 ROW14 ROW13 ROW12 ROW11 ROW10 ROW9 ROW8 ROW7 ROW6 ROW5 ROW4 ROW3 ROW2 ROW1 ROW0 ICONS
X 5285.18 5285.18 5285.18 5285.18 5285.18 5285.18 5285.18 5285.18 5285.18 5285.18 5285.18 5285.18 5285.18 5285.18 5285.18 5285.18 5285.18 5285.18 5285.18 5285.18 5285.18
Y -768.78 -692.48 -616.18 -539.88 -463.58 -387.28 -310.98 -234.68 -158.38 -82.08 -5.78 70.53 146.83 223.13 299.43 375.73 452.03 528.33 604.63 680.93 757.23
Y
PIN268 (0,0) PIN 1
PIN137 x PIN115
Die Size: 10.977mm X 1.912mm Bump Height: 18 +/- 4um (Chip to chip), 18 +/- 2um (Within chip)
X [um] 101.6
Y [um] 43.5
Pad # 137 - 268
X [um] 43.5
Y [um] 101.6
Pad # 269 - 289
X [um] 101.6
Y [um] 43.5
Gold bump size tolerance: +/-1.5um.
SSD1812 6
REV 1.2 12/99
SOLOMON
SSD1812Z Die Pad Coordinates
PAD # 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202
NAME SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 SEG42 SEG43 SEG44 SEG45 SEG46 SEG47 SEG48 SEG49 SEG50 SEG51 SEG52 SEG53 SEG54 SEG55 SEG56 SEG57 SEG58 SEG59 SEG60 SEG61 SEG62 SEG63 SEG64 SEG65
X 4997.65 4921.35 4845.05 4768.75 4692.45 4616.15 4539.85 4463.55 4387.25 4310.95 4234.65 4158.35 4082.05 4005.75 3929.45 3853.15 3776.85 3700.55 3624.25 3547.95 3471.65 3395.35 3319.05 3242.75 3166.45 3090.15 3013.85 2937.55 2861.25 2784.95 2708.65 2632.35 2556.05 2479.75 2403.45 2327.15 2250.85 2174.55 2098.25 2021.95 1945.65 1869.35 1793.05 1716.75 1640.45 1564.15 1487.85 1411.55 1335.25 1258.95 1182.65 1106.35 1030.05 953.75 877.45 801.15 724.85 648.55 572.25 495.95 419.65 343.35 267.05 190.75 114.45 38.15
Y 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98
PAD # 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268
NAME SEG66 SEG67 SEG68 SEG69 SEG70 SEG71 SEG72 SEG73 SEG74 SEG75 SEG76 SEG77 SEG78 SEG79 SEG80 SEG81 SEG82 SEG83 SEG84 SEG85 SEG86 SEG87 SEG88 SEG89 SEG90 SEG91 SEG92 SEG93 SEG94 SEG95 SEG96 SEG97 SEG98 SEG99 SEG100 SEG101 SEG102 SEG103 SEG104 SEG105 SEG106 SEG107 SEG108 SEG109 SEG110 SEG111 SEG112 SEG113 SEG114 SEG115 SEG116 SEG117 SEG118 SEG119 SEG120 SEG121 SEG122 SEG123 SEG124 SEG125 SEG126 SEG127 SEG128 SEG129 SEG130 SEG131
X -38.15 -114.45 -190.75 -267.05 -343.35 -419.65 -495.95 -572.25 -648.55 -724.85 -801.15 -877.45 -953.75 -1030.05 -1106.35 -1182.65 -1258.95 -1335.25 -1411.55 -1487.85 -1564.15 -1640.45 -1716.75 -1793.05 -1869.35 -1945.65 -2021.95 -2098.25 -2174.55 -2250.85 -2327.15 -2403.45 -2479.75 -2556.05 -2632.35 -2708.65 -2784.95 -2861.25 -2937.55 -3013.85 -3090.15 -3166.45 -3242.75 -3319.05 -3395.35 -3471.65 -3547.95 -3624.25 -3700.55 -3776.85 -3853.15 -3929.45 -4005.75 -4082.05 -4158.35 -4234.65 -4310.95 -4387.25 -4463.55 -4539.85 -4616.15 -4692.45 -4768.75 -4845.05 -4921.35 -4997.65
Y 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98 751.98
PAD # 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289
NAME ROW32 ROW33 ROW34 ROW35 ROW36 ROW37 ROW38 ROW39 ROW40 ROW41 ROW42 ROW43 ROW44 ROW45 ROW46 ROW47 ROW48 ROW49 ROW50 ROW51 ROW52
X -5285.18 -5285.18 -5285.18 -5285.18 -5285.18 -5285.18 -5285.18 -5285.18 -5285.18 -5285.18 -5285.18 -5285.18 -5285.18 -5285.18 -5285.18 -5285.18 -5285.18 -5285.18 -5285.18 -5285.18 -5285.18
Y 757.23 680.93 604.63 528.33 452.03 375.73 299.43 223.13 146.83 70.53 -5.78 -82.08 -158.38 -234.68 -310.98 -387.28 -463.58 -539.88 -616.18 -692.48 -768.78
SOLOMON
REV 1.2 12/99
SSD1812 7
MAXIMUM RATINGS* (Voltages Referenced to VSS, TA=25C)
Symbol VDD VEE Vin I TA Tstg Input Voltage Current Drain Per Pin Excluding VDD and VSS Operating Temperature Storage Temperature Range Supply Voltage Parameter Value -0.3 to +4.0 -4.0 to -12.0 VSS-0.3 to VDD+0.3 25 -30 to +85 -65 to +150 Unit V V V mA C C
* Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the limits in the Electrical Characteristics tables or Pin Description section.
This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions to be taken to avoid application of any voltage higher than maximum rated voltages to this high impedance circuit. For proper operation it is recommended that Vin and Vout be constrained to the range VSS < or = (Vin or Vout) < or = VDD. Reliability of operation is enhanced if unused input are connected to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open. This device may be light sensitive. Caution should be taken to avoid exposure of this device to any light source during normal operation. This device is not radiation protected.
ELECTRICAL CHARACTERISTICS (Voltage Referenced to VSS, VDD=1.8 to 3.5V, TA=25C; unless otherwise specified.)
Symbol VDD IAC Parameter Logic Circuit Supply Voltage Range Voltage Generator Circuit Supply Voltage Range Access Mode Supply Current Drain (VDD Pins) Test Condition Recommend Operating Voltage Possible Operating Voltage VDD = 2.7V, Voltage Generator On, 4X Converter Enabled, Write accessing, Tcyc =3.3MHz, Osc. Freq.=31kHz, Display On. VDD = 2.7V, VEE = -8.1V, Voltage Generator Disabled, R/W(WR) Halt, Osc. Freq. = 31kHz, Display On, VL6 - VDD = -8.1V. VDD = 2.7V, VEE = -8.1V, Voltage Generator On, 4x DC-DC Converter Enabled, R/W(WR) Halt, Osc. Freq. = 31kHz, Display On, VL6 - VDD = -8.1V. VDD=2.7V, LCD Driving Waveform Off, Osc. Freq. = 31kHz, R/W(WR) halt. VDD = 2.7V, LCD Driving Waveform Off, Oscillator Off, R/W(WR) halt. Display On, Voltage Generator Enabled, DC/DC Converter Enabled, Osc. Freq.=31KHz, Regulator Enabled, Divider Enabled. Voltage Generator Disabled. Iout=100A Min 2.4 1.8 Typ 2.7 300 Max 3.5 3.5 TBD A Unit V
IDP1
Display Mode Supply Current Drain (VDD Pins)
-
120
TBD
A
IDP2
Display Mode Supply Current Drain (VDD Pins)
-
150
TBD
A
ISB
Standby Mode Supply Current Drain (VDD Pins)
-
3.5
10
A
ISLEEP
Sleep Mode Supply Current Drain (VDD Pins)
-
0.2
5
A
VEE
LCD Driving Voltage Generator Output (VEE Pin)
-12.0
-
-1.8
V
VLCD VOH1
LCD Driving Voltage Input (VEE Pin) Output High Voltage (D0-D7) Output Low Voltage (D0-D7) LCD Driving Voltage Source (VL6 Pin)
-12.0 0.9*VDD
-
-1.8 VDD
V V
VOL1
Iout=100A
0
-
0.1*VDD
V
VL6
Regulator Enabled (VL6 voltage depends on Int/Ext Contrast Control) Regulator Disable
VEE-0.5
-
VDD
V
VL6
LCD Driving Voltage Source (VL6 Pin)
-
Floating
-
V
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ELECTRICAL CHARACTERISTICS (Voltage Referenced to VSS, VDD=1.8 to 3.5V, TA=25C; unless otherwise specified.)
Symbol VIH1 Input high voltage (RES, D0-D7,R/W(WR), D/C) VIL1 VL2 VL3 VL4 VL5 VL6 VL2 VL3 VL4 VL5 VL6 VL2 VL3 VL4 VL5 VL6 IOH Input Low voltage (RES, CS1,CS2, D0-D7, R/W(WR), D/C, S/P) LCD Display Voltage Output (VL2, VL3, VL4, VL5, VL6 Pins) Voltage reference to VDD, Smart Bias Divider Enabled, 1:6 bias ratio VL3 VL4 VL5 VL6 -12V 50 1/6*VL6 2/6*VL6 4/6*VL6 5/6*VL6 VL6 1/8*VL6 2/8*VL6 6/8*VL6 7/8*VL6 VL6 VDD VL2 VL3 VL4 VL5 V V V V V V V V V V V V V V V A 0 0.2*VDD V Parameter Test Condition Min 0.8*VDD Typ Max VDD Unit V
LCD Display Voltage Output (VL2, VL3, VL4, VL5, VL6 Pins)
Voltage reference to VDD, Smart Bias Divider Enabled, 1:8 bias ratio
LCD Display Voltage Input (VL2, VL3,VL4, VL5, VL6 Pins)
Voltage reference to VDD, External Voltage Generator, Smart Bias Divider Disabled
Output High Current Source (D0-D7) Output Low Current Drain (D0-D7) Output Tri-state Current Drain Source (D0-D7) Input Current (RES, D0-D7, R/W(WR), D/C, S/P) Input Capacitance (all logic pins) Variation of VL6 Output (VDD is fixed) Temperature Coefficient Compensation
Vout=VDD-0.4V
IOL
Vout=0.4V
-
-
-50
A
IOZ IIL/IIH CIN VL6
-1 -1 Regulator Enabled, Internal Contrast Control Enabled, Set Contrast Control Register = 0 Voltage Regulator Enabled Voltage Regulator Enabled Voltage Regulator Enabled Voltage Regulator Enabled Voltage Regulator Enabled Voltage Regulator Enabled Voltage Regulator Enabled Voltage Regulator Enabled -
5 3
1 1 7.5 -
A A pF %
PTC0 PTC1 PTC2 PTC3 PTC4 PTC5 PTC6 PTC7
Flat Temperature Coefficient [POR] Temperature Coefficient 1* Temperature Coefficient 2* Temperature Coefficient 3* Temperature Coefficient 4* Temperature Coefficient 5* Temperature Coefficient 6* Temperature Coefficient 7*
0 -0.075 -0.15
-0.20
-0.01 TBD -0.10 TBD -0.18 TBD TBD -0.25
-0.075 -0.15 -0.20
%/C %/C %/C %/C %/C %/C %/C %/C
* The formula for the temperature coefficient is: TC(%)= Vref at 50C - Vref at 0C X 50C - 0C 1 X100% Vref at 25C
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AC ELECTRICAL CHARACTERISTICS (TA=25C, Voltage referenced to VSS, AVDD=DVDD=3V: unless otherwise specified.)
Symbol FOSC FFRM Parameter Oscillation Frequency of Display Timing Generator Frame Frequency Test Condition Internal Oscillator Enabled Display ON, Set 132X 54 Graphic Display Mode Min 27 Typ 31 FOSC 8*55 Max 35 Unit kHz Hz
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TABLE 3. Parallel Timing Characteristics (TA=25C, VDD=2.7V, VSS=0V)
Symbol tcycle tAS tAH tDSW tDHW tDHR tOH tACC PWCSL PWCSH tR tF Clock Cycle Time Address Setup Time Address Hold Time Write Data Setup Time Write Data Hold Time Read Data Hold Time Output Disable Time Access Time Chip Select Low Pulse Width (read) Chip Select Low Pulse Width (write) Chip Select High Pulse Width (read) Chip Select High Pulse Width (write) Rise Time Fall Time Parameter Min 300 0 0 40 15 20 120 60 60 60 Typ Max 70 140 15 15 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns
R/W
D/C
tAS E tcycle PWCSL CS1 (CS2=1) tF tDSW D0-D7 (Write data to driver) tACC D0-D7 (Read data from driver) Valid Data Valid Data
tAH
PWCSH
tR tDHW
tDHR
tOH
Figure 1. Parallel 6800-series Interface Timing Characteristics
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TABLE 4. Parallel Timing Characteristics (TA=25C, VDD=2.7V, VSS=0V)
Symbol tcycle tAS tAH tDSW tDHW tDHR tOH tACC PWCSL PWCSH tR tF Clock Cycle Time Address Setup Time Address Hold Time Write Data Setup Time Write Data Hold Time Read Data Hold Time Output Disable Time Access Time Chip Select Low Pulse Width (read) Chip Select Low Pulse Width (write) Chip Select High Pulse Width (read) Chip Select High Pulse Width (write) Rise Time Fall Time Parameter Min 300 0 0 20 40 20 120 60 60 60 Typ Max 70 140 15 15 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns
D/C
tAS
tAH
WR
RD tcycle PWEL CS1 (CS2=1) tF (Read data from driver) D0-D7 (Write data to driver) tACC D0-D7 Valid Data tDSW Valid Data PWEH
tR tDHW
tDHR
tOH
Figure 2. Parallel 8080-series Interface Timing Characteristics
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TABLE 5. Serial Timing Characteristics (TA=25C, DVDD=2.7V, VSS=0V)
Symbol tcycle tAS tAH tCSS tCSH tDSW tDHW tCLKL tCLKH tR tF Clock Cycle Time Address Setup Time Address Hold Time Chip Select Setup Time Chip Select Hold Time Write Data Setup Time Write Data Hold Time Clock Low Time Clock High Time Rise Time Fall Time Parameter Min 400 250 250 250 250 150 150 150 150 Typ Max 15 15 Unit ns ns ns ns ns ns ns ns ns ns ns
D/C tAS CS1 (CS2=1) tCSS tcycle tCLKL SCK tF tDSW SDA Valid Data tR tDHW tCLKH tAH tCSH
Figure 3. Serial Timing Characteristics
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PIN DESCRIPTIONS
M/S This pin is master/slave mode selection input. When this pin is pulled high, master mode is selected and CL, M, MSTAT and DOF will be output to slave devices. When pulled low, slave mode is selected. CL, M, DOF are required to be input from master device while MSTAT is high impedance. M This pin is the frame signal input/output. In master mode, the pin supplies frame signal to slave devices while in slave mode, the pin receives frame signal from the master device. MSTAT This pin is used together with M in master operation for static drive output. It becomes high impedance in slave mode operation. CL This pin is the display clock input/output. In master mode, the pin supplies display clock signal to slave devices while in slave mode, the pin receives display clock signal from the master device. DOF This pin is LCD blanking control input/output. In master mode, the pin supplies on/off signal to slave devices. In slave mode, the pin receives on/ off signal from the master device. CLS This pin is a internal clock enable input pin. When this pin is high, the internal clock is enabled. The internal clock will be disabled when it is low, an external clock should be input to CL pin. RES This pin is reset signal input. When the pin is low, initialization of the chip is executed. P/S This pin is serial/parallel interface select input. When P/S is high, parallel mode is selected and when P/S is low, serial mode is selected. In serial mode, only write operation is allowed. CS1, CS2 These pin are chip select inputs. The chip is enabled for data operation only when CS1 is low and CS2 is high. C68/80 This pin is microprocessor interface select input. When the pin is high, 6800 series interface is selected and when the pin is low, 8080 series interface is selected. D0-D7 These pins are 8-bit bi-directional data bus to be connected to the microprocessor' data bus. When serial mode is selected, D7 is the serial data s input SDA and D6 is the serial clock input SCK. D/C This pin is control/display data input control flag. When the pin is high, the data on D0-D7 is display data. When the pin is low, the data on D0-D7 is control data. R/W(WR) This pin is microprocessor interface signal. When interfacing to an 6800series microprocessor, the signal indicates read mode when high and write mode when low. When interfacing to an 8080-microprocessor, a data write operation is initiated when R/W(WR) is low and the chip is selected. E(RD) This pin is microprocessor interface signal. When interfacing to an 6800series microprocessor, a data operation is initiated when E(RD) is high and the chip is selected. When interfacing to an 8080-microprocessor, a data read operation is initiated when E(RD) is low and the chip is selected.
VDD Power supply pin. VSS Ground. VSS1 Reference voltage input for internal DC-DC converter. The voltage of generated VEE equals to the multiple factor (2X, 3X or 4X) times the protential different between this pin, VSS1, and VDD. All generated voltage is referenced toVDD. Note: voltage at this input pin must less than or equal to VSS. VEE This is the most negative voltage supply pin of the chip. It can be supplied externally or generated by the internal DC-DC converter. When using internal DC-DC converter as generator, voltage at this pin is for internal reference only. It CANNOT be used for driving external circuitries. C3N, C1P, C1N, C2P and C2N When internal DC-DC voltage converter is used, external capacitor(s) is/are connected among these pins. VL6 This pin is the most negative LCD driving voltage. It can be supplied externally or generated by the internal regulator. VF This pin is an input of the internal voltage regulator. When internal regulator is used to generate VL6, external resistors are connected between VDD and VF, and VF and VL6, respectively (see application circuit). VFS This pin is an input to provide an external voltage reference for the internal voltage regulator. It is only enabled in External Input chip options. IRS This pin is an input pin to enable the internal resistors network for the voltage regulator when IRS is high. When it is low, the external resistors R1/R2 should be connected to VL6 and VF. HPM This pin is an input pin to enable the high power current mode when it is low. The contrast curves in High Power Mode will be different to Normal Mode. Details of the High Power Mode Contrast curve is TBD. VL2, VL3, VL4 and VL5 (Voltages referenced to VDD) LCD driving voltages. They can be supplied externally or generated by the internal smart bias divider. They have the following relationship: VDD > VL2 > VL3 > VL4 > VL5 > VL6 1:6 bias VL2 VL3 VL4 VL5 1/6*VL6 2/6*VL6 4/6*VL6 5/6*VL6 1:8 bias 1/8*VL6 2/8*VL6 6/8*VL6 7/8*VL6
ROW0 - ROW63 These pins provide the row driving signal COM0 - COM53 to the LCD panel. See Table.1 about the COM signal mapping in different multiplex ratio N. ICONS This pin is the special icons line. SEG0 - SEG131 These pins provide the LCD column driving signal. Their voltage level is VDD during sleep mode and standby mode.
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OPERATION OF LIQUID CRYSTAL DISPLAY DRIVER Description of Block Diagram Module
Command Decoder and Command Interface This module determines whether the input data is interpreted as data or command. Data is directed to this module based upon the input of the D/C pin. If D/C is high, data is written to Graphic Display Data RAM (GDDRAM). If D/C is low, the input at D0-D7 is interpreted as a Command and it will be decoded and written to the corresponding command register. Reset is of the same function as Power ON Reset (POR). Once RES receives a negative reset pulse of about 1us, all internal circuitry will be back to its initial status. Refer to Command Description section for more information. MPU Parallel 6800-series Interface The parallel interface consists of 8 bi-directional data pins (D0-D7), R/W(WR), D/C, E(RD), CS1 and CS2. R/W(WR) input High indicates a read operation from the Graphic Display Data RAM (GDDRAM) or the status register. R/W(WR) input Low indicates a write operation to Display Data RAM or Internal Command Registers depending on the status of D/C input. The E(RD) input serves as data latch signal (clock) when high provided that CS1 and CS2 are low and high respectively. Refer to Figure 1 of parallel timing characteristics for Parallel Interface Timing Diagram of 6800-series microprocessors. In order to match the operating frequency of display RAM with that of the microprocessor, some pipeline processing is internally performed which requires the insertion of a dummy read before the first actual display data read. This is shown in Figure 4 below. MPU Parallel 8080-series interface The parallel interface consists of 8 bi-directional data pins (D0-D7), E(RD), R/W(WR), D/C, CS1 and CS2. E(RD) input serves as data read latch signal (clock) when low provided that CS1 and CS2 are low and high respectively. Whether it is display data or status register read is controlled by D/C. R/W(WR) input serves as data write latch signal(clock) when high provided that CS1 and CS2 are low and high respectively. Whether it is display data or command register write is controlled by D/C. Refer to Figure 2 of parallel timing characteristics for Parallel Interface Timing Diagram of 8080-series microprocessor. Similar to 6800-series interface, a dummy read is also required before the first actual display data read. MPU Serial interface The serial interface consists of serial clock SCK, serial data SDA, D/C, CS1 and CS2. SDA is shifted into a 8-bit shift register on every rising edge of SCL in the order of D7, D6,... D0. D/C is sampled on every eighth clock and the data byte in the shift register is written to the Display Data RAM or command register in the same clock.
R/W(WR)
E(RD)
data bus
N write column address dummy read
n data read1
n+1 data read 2
n+2 data read 3
Figure 4: display data read with the insertion of dummy read
Graphic Display Data RAM (GDDRAM) The GDDRAM is a bit mapped static RAM holding the bit pattern to be displayed. The size of the RAM is 132 x 65= 8580 bits. Figure 5 is a description of the GDDRAM address map. For mechanical flexibility, re-mapping on both Segment and Common outputs are pro-
vided. For vertical scrolling of display, an internal register storing the display start line can be set to control the portion of the RAM data to be mapped to the display. Figure 5 shows the case in which the display start line register is set at 38H.
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Column address 00H (83H) Segment Remap Enabled LSB [D0] Page 0 MSB [D7] LSB Page 1 MSB LSB Page 2 MSB LSB Page 3 MSB LSB Page 4 MSB LSB Page 5
Column address 83H (00H) COM SCAN MODE NORMAL (REMAPPED) COM8 (COM45)
COM53 (COM0) MSB LSB Page 6 MSB LSB Page 7 MSB Page 8 (LSB) COM7 (COM46) ICONS
38H
COM0 (COM53)
SEG0
SEG131
Note:
The configuration in parentheses represent the non-remapping of Rows and Columns
Figure 5. Graphic Display Data RAM (GDDRAM) Address Map (with display start line value 38H) For 132 X 54 Graphic Display Mode
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Oscillator Circuit This module is an On-Chip low power RC oscillator circuitry (Figure 6). The oscillator generates the clock for the DC-DC voltage converter. This clock is also used in the Display Timing Generator.
Oscillator enable (CLS) enable Oscillation Circuit enable Buffer (CL)
OSC1 Internal pwell resistor
OSC2
Figure 6. Oscillator Circuitry
LCD Driving Voltage Generator and Regulator This module generates the LCD voltage needed for display output. It takes a single supply input and generate necessary bias voltages. It consists of: 1. 2X, 3X and 4X DC-DC voltage converter Please refer to application notes. 2. Voltage Regulator (Voltages referenced to VDD) Feedback gain control for initial LCD voltage. External resistors are connected between VDD and VF, and between VF and VL6. These resistors are chosen to give the desired VL6 according to the following equation: VL6 = (1 + R2/R1)Vref where Vref is the internally generated reference voltage with a known R1 and R2, and Vref can be calculated by a measured VL6. R1 and R2 are the resistance values of the resistors between VDD and VF, and VF and VL6, respectively. 3. Smart Bias Divider Divide the regulator output to give the LCD driving voltages (VL2 VL5). This is a low power consumption circuit which saves most of the display current. 4. Contrast Control (Voltages referenced to VDD) Software control of 64 voltage levels of LCD voltage. 5. Bias Ratio Selection circuitry Software control of 1/6 and 1/8 bias ratio to match the characteristic of LCD panel. In addition, 1/4, 1/5, 1/7 and 1/9 bias ratios are software selectable for any mux application. 6. Self adjust temperature compensation circuitry Provide 8 different compensation grade selections to satisfy the various liquid crystal temperature grades. The grading can be selected by software control. Defaulted temperature coefficient (TC) value is -0.05%/oC.
Level Selector Level Selector is a control of the display synchronization. Display voltage can be separated into two sets and used with different cycles. Synchronization is important since it selects the required LCD voltage level to the HV Buffer Cell, which in turn outputs the COM or SEG LCD waveform. HV Buffer Cell (Level Shifter) HV Buffer Cell works as a level shifter which translates the low voltage output signal to the required driving voltage. The output is shifted out with an internal FRM clock which comes from the Display Timing Generator. The voltage levels are given by the level selector which is synchronized with the internal M signal. Reset Circuit When RES input is low, the chip is initialized with the following status: 1. Display is OFF 2. 132x48 [Not included ICONS line] Display Mode 3. Normal segment and display data column address mapping (SEG0 mapped to address 00H) 4. Read-modify-write mode is OFF 5. Power control register is set at 000B. 6. Shift register data clear in serial interface 7. Bias ratio is set at 1/8 8. Static indicator is OFF 9. Display start line is set at display RAM address 0 10. Column address counter is set at 0 11. Page address is set at 0 12. Normal scan direction of the COM outputs 13. Internal Regulator Resistor Ratio at 4 14. Contrast control register is set at 20H 15. Test mode is OFF 16. Temperature Coefficient is set to PTC0
187 Bit Latch A register carries the display signal information. In 132 X 55 display mode. Data will be fed to the HV-buffer Cell and level-shifted to the required level.
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LCD Panel Driving Waveform
The following is an example of how the Common and Segment drivers may be connected to a LCD panel. The waveforms shown in Figure 7a and 7b illustrate the desired multiplex scheme.
COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 SEG0 SEG1 SEG2 SEG3 SEG4
Figure 7a. LCD Display Example "0"
TIME SLOT
123456789 * . . . N+1 1 2 3 4 5 6 7 8 9 * . . . N+1 1 2 3 4 5 6 7 8 9 * . . . N+1 1 2 3 4 5 6 7 8 9 * . . . N+1
VDD VL2 COM0 VL3 VL4 VL5 VL6
VDD VL2 COM1 VL3 VL4 VL5 VL6
VDD VL2 SEG0 VL3 VL4 VL5 VL6
VDD VL2 SEG1 VL3 VL4 VL5 VL6 M
* Note : N is the number of multiplex ratio not included Icon, N is equal to 54 on POR.
Figure 7b. LCD Driving Signal from SSD1812
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Command Description
Set Display On/Off This command alternatively turns the display on and off. When display off is issued with entire display on, power save mode will be entered. See " Set Power Save Mode" for details. Set Display Start Line This command is to set Display Start Line register to determine starting address of display RAM to be displayed by selecting a value from 0 to 63. With value equals to 0, D0 of Page 0 is mapped to COM0. With value equals to 1, D1 of Page0 is mapped to COM0. The display start line values of 0 to 63 are assigned to Page 0 to 7. Set Page Address This command positions the page address to 0 to 8 possible positions in GDDRAM. Refer to figure 5. Set Higher Column Address This command specifies the higher nibble of the 8-bit column address of the display data RAM. The column address will be incremented by each data access after it is pre-set by the MCU. Set Lower Column Address This command specifies the lower nibble of the 8-bit column address of the display data RAM. The column address will be incremented by each data access after it is pre-set by the MCU. Set Segment Re-map This commands changes the mapping between the display data column address and segment driver. It allows flexibility in layout during LCD module assembly. Refer to figure 5. Set Normal/Reverse Display This command sets the display to be either normal/reverse. In normal display, a RAM data of 1 indicates an " ON"pixel while in reverse display, a RAM data of 0 indicates an " ON"pixel. In icon mode, the icon line is not reversed by this command. Set Entire Display On/Off This command forces the entire display, including the icon row, to be " ON" regardless of the contents of the display data RAM. This command has priority over normal/reverse display. This command will be used with " Set Display Display ON/OFF" command to form a compound command for entering power save mode. See " Set Power Save Mode" . Set LCD Bias This command selects a suitable bias ratio (1/6 or 1/8) required for driving the particular LCD panel in use. The POR default for SSD1812 is set to 1/8 bias. For setting 1/4, 1/5, 1/7 and 1/9 bias, an extended compound command should be used. Set Read-Modify-Write Mode This command puts the chip in read-modify-write mode in which: 1. the column address is saved before entering the mode 2. the column address is incremented by display data write but not by display data read Set End of Read-Modify-Write Mode This command relieves the chip from read-modify-write mode. The column address that is saved before entering read-modify-write mode will be restored.
Software Reset This command causes some of the internal status of the chip to be initialized: 1. Display is OFF 3. Normal segment and display data column address mapping (SEG0 mapped to address 00H) 4. Read-modify-write mode is OFF 5. Power control register is set at 0 6. Bias ratio is set at 1/8 7. Static indicator is OFF 8. Display start line is set at display RAM address 0 9. Column address counter is set at 0 10. Page address is set at 0 11. Normal scan direction of the COM outputs 12. Internal Regulator Resistor Ratio at 4 13. Contrast control register is set at 20H 14. Test mode is OFF Set COM Output Scan Direction This command sets the scan direction of the COM output allowing layout flexibility in LCD module assembly. Set Power Control Register This command turns on/off the various power circuits associated with the chip. Set Internal Regulator Resistors Ratio This command is to enable any one of the eight internal resistor sets for different regulator gain when using internal regulator resistor network (IRS pin pulled high). The relationship between the VL6 and the 64 levels of contrast step is TBD. Internal Contrast Registor 3FH 00H 20H
Internal Regulator Resistors Ratio Command: 00100X2X1X0
0 VL6 [V]
X2X1X0 000
D
001 010 011 1 0 0 (POR) 101 110 111
-12V
Set Contrast Control Register This commands adjusts the contrast of the LCD panel by changing VL6 of the LCD drive voltage provided by the On-Chip power circuits. VL6 is set with 64 steps (6-bit) contrast control register. It is a compound commands:
TB
No
Set Contrast Control Register Contrast Level Data Changes Complete? Yes
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Set Indicator On/Off This command turns on and off the static drive indicators. It also controls whether standby mode or sleep mode will be entered after the power save compound command. See " Set Power Save Mode" . When the " Set Indicator On" command is sent, the " Indicator Display Mode" must be followed in the next command. The " Set Indicator Off" command is a single byte command and no following command is required. Set Power Save Mode To enter Standby or Sleep Mode, it should be done by using a compound command composed of " Set Display ON/OFF" and " Set Entire Display ON/OFF" commands. When " Set Entire Display ON" is issued during display is OFF, either Standby Mode or Sleep Mode will be entered. The status of the Static Indicator will determine which power save mode is entered. If static indicator is off, the Sleep Mode will be entered: 1. Internal oscillator and LCD power supply circuits are stopped 2. Segment and Common drivers output VDD level 3. The display data and operation mode before sleep are held 4. Internal display RAM can still be accessed If the static indicator is on, the chip enters Standby Mode which is similar to sleep mode except: 1. the internal oscillator is on 2. the static drive system is on Note also that if the software reset command is issued during Standby Mode, Sleep Mode will be entered. Both power save modes can be exited by the issue of a new software command or by pulling Low at hardware pin RES. NOP No Operation Command Set Test Mode This command force the driver chip into its test mode for internal testing of the chip. Under normal operation, user should NOT use this command. Status register Read This command is issued by setting D/C Low during a data read (refer to figure 1 and 2 parallel interface waveform). It allows the MCU to monitor the internal status of the chip. No status read is provided for serial mode. EXTENDED COMMANDS These commands are used, in addition to basic commands, to trigger the enhanced features, on top of general ones, designed for the chip. Set Multiplex Ratio This command switches default 54 multiplex mode to any multiplex mode from 1 to 54. The chip pads ROW0-ROW63 will be switched to corresponding COM signal output, see Table 1. Set RAM Page Blinking Freq. This command sets the blinking frequency of blinking page(s) which is set using the " Set RAM Page Blinking" extended command. Set Bias Ratio Except the 1/4 bias, all the available bias ratio (1/5, 1/6, 1/7, 1/8, 1/9) could be set using this command. When changing the display multiplex ratio, the bias ratio also need to be adjusted to make display contrast consistent.
Set Temperature Coefficient (TC) Value This command is to set 1 out of 8 different temperature coefficients in order to match various liquid crystal temperature grades. Set 1/4 Bias Ratio This command sets the bias ratio directly to 1/4 bias. This ratio is especially for use in under 12mux display. In order to restore to other bias ratio, this command must be executed, with LSB=0, before the " Set Multiplex ratio" or " Set LCD Bias" command is sent. Set Display Offset This command should be sent ONLY when the multiplex ratio is set less than 54. When the mulitplex ratio less than 54 is set, the display will be mapped in the middle (y-direction) of the LCD, see Table 1. Use this command could move the display vertically within the 54 commons. To make the Reduced-Mux Com 0 (Com 0 after reducing the multiplex ratio) towards the Row 0 direction for L lines, the 6-bit data in second command should be given by L. To move in the other direction by L lines, the 6-bit data should be given by 64-L. Please note that the display is confined within the un-reduced 54 mux. That is maximum value of L is given by the half of 54 minus the reducedmultiplex ratio. For an odd display mux after reduction, moving away from Row 0 direction will has 1 more step. Set Smart Icon Mode This command is used to enter/leave the Smart Icon Mode. In Smart Icon Mode, Entire display will be turned off except the Icon row. Set RAM Page Blinking This command enable the whole page to blink in the frequency set by " Set RAM Page Blinking Freq."command. Setting either bit(s) in the data given in the second command will force cooresponding page to blink. LSB of the data points to Page 0 and so on to MSB for Page 7.
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COMMAND TABLE
Bit Pattern 1010111X0 01X5X4X3X2X1X0 Write Command (D/C=0, R/W(WR)=0, E(RD)=1) Set Display On/Off Set Display Start Line X0=0: turns off LCD panel (POR) X0=1: turns on LCD panel Set display RAM display start line register from 0-63 using X 5X 4X 3X 2X 1X 0. Display start line register is reset to 000000 during POR. 1011X3X2X1X0 0001X3X2X1X0 Set Page Address Set Higher Column Address Set GDDRAM Page Address (0-8) using X3X2X1X 0 Set the higher nibble of the colume address register using X3X2X1X0 as data bits. The initial display line register is reset to 0000 during POR. Set the lower nibble of the colume address register using X3X2X1X0 as data bits. The initial display line register is reset to 0000 during POR. X0=0: column address 00H is mapped to SEG0 (POR) X0=1: column address 83H is mapped to SEG0 Refer to Fig. 5 for details. 1010011X0 1010010X0 1010001X0 Set Normal/Reverse Display Set Entire Display On/Off Set LCD Bias X0=0: normal display (POR) X0=1: reverse display X0=0: normal display (POR) X0=1: entire display on X0=0: 1/8 bias (POR) X0=1: 1/6 bias For setting bias ratio to 1/4, 1/5, 1/7 or 1/9, see Extended Command Table. Read-modify-write mode will be entered in which the column address will not be incremented during display data read Exit Read-modify-write mode. Column address before entering the mode will be restored Initialize the internal status X3=0: normal mode (POR) X3=1: remapped mode. COM0 to COM[N-1] becomes COM[N-1] to COM0 in Multiplex ratio is equal to N. See Fig.5 as an example for N equal to 54. X0=0: turns off the output op-amp buffer (POR) X0=1: turns on the output op-amp buffer X1=0: turns off the internal regulator (POR) X1=1: turns on the internal regulator X2=0: turns off the internal voltage booster (POR) X2=1: turns on the internal voltage booster Internal regulator gain increases as X2X1X0 increased from 000b to 111b. X2X 1X 0 = 100b (POR) Set Contrast level from 64 contrast steps. Contrast increases as X5X4X3X2X1X0 is increased. X5X4X3X2X1X0 = 100000b (POR) X0 = 0: indicator off (POR, no need of second command byte) X0 = 1: indicator on (second command byte required) Comment
0000X3X2X1X0
Set Lower Column Address
1010000X0
Set Segment Re-map
11100000 11101110 11100010 1100X3 * * *
Set Read-Modify-Write Mode Set End of Read-Modify-Write Mode Software Reset Set COM Output Scan Direction
00101X2X1X0
Set Power Control Register
00100X2X1X0 10000001 * * X 5X 4X 3X 2X 1X 0 1010110X0
Set Internal Regulator Resistor Ratio Set Contrast Control Register
Set Indicator On/Off
* * * * * * X1X 0
X1X0 = 00: indicator off X1X0 = 01: indicator on and blinking at ~1 second interval This second byte command is required X X = 10: indicator on and blinking at ~1/2 second interval 10 ONLY when " Set Indicator On" com- X1X0 = 11: indicator on constantly mand is sent. Indicator Display Mode, Set Power Save Mode NOP Set Test Mode Test Mode Reset Standby or sleep mode will be entered with compound commands Command for No Operation Reserved for IC testing. Do NOT use. Reserved for IC testing. Do NOT use.
******** 11100011 1111 * * * * 11110000
SOLOMON
REV 1.2 12/99
SSD1812 21
Bit Pattern D7D6D5D4D3D2D1D0 (Data Read Back from the driver)
Read Command (D/C=0, R/W(WR)=1, E(RD)=0) Status Register Read
Comment D7=0: indicates an internal operation is completed. D7=1: indicates an internal operation is in progress. D6=0: indicates normal segment mapping with column address D6=1: indicates reverse segment mapping with column address D5=0: indicates the display is ON D5=1: indicates the display is OFF D4=0: initialization is not in progress D4=1: initialization is in progress after RES or software reset D3D2D1D0 = 1010, these 4-bit is fixed to 1010 which could be used to identify as Solomon Systech Device.
Data Read / Write
To read data from the GDDRAM, input High to R/W(WR) pin and D/C pin for 6800-series parallel mode, Low to E(RD) pin and High to D/ C pin for 8080-series parallel mode. No data read is provided for serial mode. In normal mode, GDDRAM column address pointer will be increased by one automatically after each data read. However, no automatic increase will be performed in read-modify-write mode. Also, a dummy read is required before the first data read. See Figure 4 in Functional Description. To write data to the GDDRAM, input Low to R/W(WR) pin and High to D/C pin for 6800-series parallel mode. For serial interface, it will always be in write mode. GDDRAM column address pointer will be increased by one automatically after each data write.
Address Increment Table (Automatic)
D/C 0 0 1 1 R/W(WR) Comment 0 1 0 1 Write Command Read Status Write Data Read Data Address Increment No No Yes Yes *1 Remarks
Address Increment is done automatically after data read write. The column address pointer of GDDRAM*2 is affected. Remarks: *1. If read data is issued in read-modify-write mode, address increase is not applied. *2. Column Address will NOT wrap round when overflow.
Commands Required for R/W(WR) Actions on RAM
R/W(WR) Actions on RAMs Read/Write Data from/to GDDRAM. Commands Required Set GDDRAM Page Address Set GDDRAM Column Address Read/Write Data Save/Restore GDDRAM Column Address. (1011X 3X 2X 1X 0)* (0001X 3X 2X 1X 0)* (0000X 3X 2X 1X 0) (X7X6X 5X 4X 3X 2X 1X 0) Save GDDRAM Column Address by read-modify- (11100000) write mode Restore GDDRAM Column Address by end of read- (11101110) modify-write mode * No need to resend the command again if it is set previously. The read / write action to the Display Data RAM does not depend on the display mode. This means the user can change the RAM content whether the target RAM content is being displayed or not.
SSD1812 22
REV 1.2 12/99
SOLOMON
EXTENDED COMMAND TABLE
Bit Pattern 10101000 X 7X 6X 5X 4X 3X 2X 1X 0 X7X6 : Set RAM Page Blinking Freq. Command X5X4X 3X 2X 1X 0 : Set Multiplex Ratio Comment To select multiplex ratio N from 2 to 55 [Included Icon Line]. N = X 5X 4X 3X 2X 1X 0 + 2, eg. N = 110101b + 2 = 55 (POR) X7X 6 = 00: 1.00sec (POR) X7X 6 = 01: 0.50sec X7X 6 = 10: 0.25sec X7X 6 = 11: always off 10101001 010X4X3X2X1X0 X1X0 : Set Bias Ratio X1X 0 = 00: 1/8, 1/6 (POR) X1X 0 = 01: 1/6, 1/5 X1X 0 = 10: 1/9, 1/7 X1X 0 = 11: Prohibited X4X3X 2: Set TC Value X4X 3X 2 = 000: -0.01%/C (POR) X4X 3X 2 = 001: Reserved X4X 3X 2 = 010: -0.10%/C X4X 3X 2 = 011: Reserved X4X 3X 2 = 100: -0.18%/C X4X 3X 2 = 101: Reserved X4X 3X 2 = 110: Reserved X4X 3X 2 = 111: -0.25%/C 1010101X0 11010010 X 7X 6X 5X 4X 3X 2X 1X 0 11010011 00X5X4X3X2X1X0 X5X4X 3X 2X 1X 0: Set Display Offset After POR, X5X4X3X2X1X0 = 0 (for mux ratio has been After setting mux ratio less than 54, data will be displayed at Center set less than 54 only) of matrix. See Table 1. To move display towards Row 0 by L, X5X4X3X2X1X 0 = L To move display away from Row 0 by L, X5X4X3X2X1X 0 = 64-L Note: max. value of L = (54 - display mux)/2 1101000X0 11010100 X 7X 6X 5X 4X 3X 2X 1X 0 11010101 X 7X 6X 5X 4X 3X 2X 1X 0 Set RAM Page Blinking After POR, X7X6X5X4X3X2X 1X 0 = 00h Set either bit to " will set cooresponding page (0-7) to blink. 1" X0: Set Smart Icon Mode Set Test Mode X0 = 0: Normal display mode (POR) X0 = 1: Smart Icon Mode Reserved for IC testing. Do NOT use. X0: Set 1/4 Bias Ratio Set Test Mode X0 = 0: use original setting (POR) X0 = 1: fixed 1/4 bias Reserved for IC testing. Do NOT use.
SOLOMON
REV 1.2 12/99
SSD1812 23
Application Circuit: External VEE with internal regulator and divider mode [Command: 2B] in 54 Mux.
ICONS COM0 : COM5 COM6 : COM25 COM26
DISPLAY PANEL SIZE 132 x 54+ 2 X ICON LINES
COM27 COM28 : : : COM53 ICONS
SEG0 --------------------------------------------- SEG131
Segment Remapped [Command: A1] COM27 COM28 COM29 : : : : : : : : COM46 COM47 SEG131 --------------------------------------------------------------------------------------------------------------------------------SEG0 ICONS COM0 : COM4 COM5 COM6 COM7 : : : COM18 COM19
Remapped COM SCAN Direction [Command: C8]
SSD1812 IC
54 MUX [Default] ( DIE FACE UP)
COM20 : COM26 ROW27 : ROW31 ICONS ROW63 : ROW59 COM53 : COM48
Remapped COM SCAN Direction [Command: C8]
VDD VL2 VL3 VL4 VL5 VL6
[Command: C8] SCAN Direction Remapped COM
N/C
VF
N/C
Remapped COM SCAN Direction [Command: C8]
R2 RESET /CS1 VSS[GND] D0 - D7 VEE R/W D/C IRS
0.1F
-
0.47F
R1 Optional for External Resistors Gain Control [IRS pulled to GND]
VDD=2.75V External Vneg=-9.5V
SSD1812 24
REV 1.2 12/99
SOLOMON
Application Circuit: ALL internal power mode [Command: 2F] in 54 Mux [Default].
ICONS COM0 : COM5 COM6 : COM25 COM26
DISPLAY PANEL SIZE 132 x 54+ 2 X ICON LINES
COM27 COM28 : : : COM53 ICONS
SEG0 --------------------------------------------- SEG131
Segment Remapped [Command: A1] COM27 COM28 COM29 : : : : : : : : COM46 COM47 SEG131 --------------------------------------------------------------------------------------------------------------------------------SEG0 ICONS COM0 : COM4 COM5 COM6 COM7 : : : COM18 COM19
Remapped COM SCAN Direction [Command: C8]
SSD1812 IC
54 MUX [Default] ( DIE FACE UP)
COM20 : COM26 ROW27 : ROW31 ICONS ROW63 : ROW59 COM53 : COM48
Remapped COM SCAN Direction [Command: C8]
VSS VEE C3N C1P C1N C2N C2P
VDD VL2 VL3 VL4 VL5 VL6
[Command: C8] SCAN Direction Remapped COM
N/C
VF
N/C
Remapped COM SCAN Direction [Command: C8]
R2 D0 - D7 and Control Bus
1F 1F 1F 1F 0.1F
-
0.47F
R1
VSS [GND]
VDD=2.75V
Optional for External Resistors Gain Control [IRS pulled to GND]
SOLOMON
REV 1.2 12/99
SSD1812 25
PACKAGE DIMENSIONS SSD1812T TAB PACKAGE DIMENSION - 1 (DO NOT SCALE THIS DRAWING)
SSD1812 26
REV 1.2 12/99
SOLOMON
PACKAGE DIMENSIONS SSD1812T TAB PACKAGE DIMENSION - 2 (DO NOT SCALE THIS DRAWING)
SOLOMON
REV 1.2 12/99
SSD1812 27
Solomon reserves the right to make changes without further notice to any products herein. Solomon makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Solomon assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. " Typical"parameters can and do vary in different applications. All operating parameters, including " Typicals" must be validated for each customer application by customer' technical experts. Solomon does not cons vey any license under its patent rights nor the rights of others.Solomon products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of unintended or unauthorized application, Buyer shall indemnify and hold Solomon and its offices, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Solomon was negligent regarding the design or manufacture of the part.
SSD1812

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